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preliminary information ? 1998 zarlink semiconductor, inc. 1 rev.2.1 C february, 1999 distinctive characteristics 8 10mbps ethernet access ports 9 direct interface with 10baset transceiver 0.5 micron 3.3 volt cmos process 352-bga package operating frequency 9 -33 33 mhz maximum 9 -40 40 mhz maximum 9 -50 50 mhz maximum 9 -66 66.66 mhz maxi- mum 32-bit local buffer memory interface 9 supports 128k to 1m bytes 9 utilize high performance 32-bit synchronous burst sram hardware assisted buffer and queue management 16-bit management bus i/o interface 9 allows host to access control registers & local buffer memory 9 big and little endian cpus 9 direct interface to standard micro- processors, including 386, 486 families and motorola mpc series embedded processors 32-bit xpressflow bus interface 9 uses granule for frame transfer- ring be tween access controllers unicast, multicast, and broadcast frames 9 also detects ieee 802.3x mac control frames works together with sc-220 xpress- flow engine 9 forwards frames at full line-rate 9 distributed flow caching? to re- duce frame forwarding latency half and full duplex operation programmable flow control 9 jam collision for half duplex mode 9 transmit flow control frame for ieee 802.3x full duplex mode supports store-&-forward frame forward- ea218e C 8-port ethernet access co n troller xpressflow 2020 ethernet routing switch chipset local buffer memory management bus xpressflow bus 16 32 32 ea-218e 8-port ethernet access controller 10baset phyiscal layer transceiver port 1 port 7 port 6 port 5 port 4 port 3 port 2 port 0 8 10baset ports block diagram- ea218e 8-port ethernet access controller general description the ea-218e provides eight 10mbps ethernet network access interface ports. the ea-218e provides the ethernet mac protocols, handles the local buffer memory interface and management, arbitrates among multiple priority queues, and interfaces with the xpressflow engine and other access controllers through the xpressflow message passing protocol. related components: sc220 C xpressflow engine ea218 C 6-port 10 + 2-port 10/100 ethernet access controller ea234 C 4-port 10/100mbps ethernet access controller
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 2 rev.2.1 C february, 1999 ing mode characteristics continue 9 automatically selects the opti- mized mode for forwarding 9 allows manual frame forwarding mode selection override multi-media ready with qos supports 9 four frame transmission priority queues complies with ieee 802.1 bridge standard 9 assigns one unique mac address for each port vlan id tagging & stripping 9 auto padding if necessary after stripping automatic retry frame transmission 9 transmit collision 9 transmit buffer under-run automatic receive filtering for bad frames for store & forward mode 9 bad fcs 9 short events or frames under 64 bytes 9 long events or frames over 1518/1522 bytes automatic statistic collection for rmon local buffer memory management bus xpressflow bus xpressflow bus interafce mac port #0 to #7 port 0 2 3 16 32 32 4567 management bus interafce local buffer memory interface automatic buffer manager mac interface 8-port 10baset phy 1 port 0 2 3 4567 1 32 32 ea-218e block diagram C ea218e 8-port ethernet access controller typical application : 9 a 16-port ethernet switch with 4-fast ethernet address mapping table flash rom sc220 x pressflow engine ea218e 8-port ethernet access controller management bus buffer ram switch manager cpu dram rs232 local control console buffer ram 8 ethernet ports buffer ram 8 ethernet ports xpressflow bus ea218e 8-port ethernet access controller buffer ram four 100m fast ethernet ports ea234 4-port ethernet access controller system block diagram -- 16-port ethernet switch with 4 fast ethernet up-links
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 3 rev.2.1 C february, 1999 1. pin assignment 1.1 logic symbol ea-218e t_mode xpressflow bus interface management bus interface test pin p_d[15:0] p_cs# p_ads# p_rwc p_bs16# p_rdy# p_int p_rst# p_clk p_a[11:1] control buffer memory interface port [7:0] 10m serial interface tm_rxd tm_rxc tm_txc tm_txen tm_txd tm_lpbk tm_fd tm_col tm_crs tm_lnk s_d[31:0] s_msgen# s_eof# s_irdy s_tabt# s_ovld# s_hpreq# s_req# s_gnt# s_clk l_d[31:0] l_oe[3:0]# l_adsc# l_clk l_a[18:2] l_we[3:0]# l_bwe[3:0]# 4 4 4
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 4 rev.2.1 C february, 1999 1.2 pin assignment ( preliminary) note: # active low signal input input signal in-st input signal with schmitt-trigger output output signal (tri-state driver) out-od output signal with open-drain driver i/o-ts input & output signal with tri-state driver i/o-od input & output signal with open-drain driver 5vt input with 5v tolerance output signal with programmable polarity. input or output pins with weak internal pull up resistors (50k to 100k ohms each) these pins are reserved for internal use only. they should be left unconnected. pin no(s). symbol type max i ol / i oh name and functions management bus interface j25,k26,l24,k25,l26, m24,l25,m26,n24,m25, p24,n26,n25,r24,p26, p25 p_d[15:0] ttl i/o-ts (5vt) 16ma management bus C data bit [15:0] c26,d24,c25,e24,d26, d25,f24,e26,e25,g24, f26 p_a[11:1] ttl in (5vt) management bus C address bit [11:1] f25 p_ads# ttl in (5vt) management bus C address strobe h25 p_rwc ttl in (5vt) management bus C read/write control j24 p_rdy# ttl out-od 16ma management bus C data ready g25 p_bs16# ttl out-od 16ma management bus C 16 bit data bus g26 p_cs# ttl in (5vt) management bus C chip select h26 p_int cmos output 4ma management bus C interrupt request j26 p_rst# ttl in-st (5vt) management bus C master reset k24 p_clk ttl in (5vt) management bus C bus clock xpressflow bus interface c23,a23,b22,c22,a22 s_d[31:27] / p_c[0:4] cmos i/o-ts 12 ma xpressflow bus C data bit [31:27] or manage- ment bus interface configuration bit [0:4] b21,d20,c21,a21,b20, a20,c20,b19,a19,c19, b18,a18,b17,c18,a17, d17,b16,c17,a16,b15, a15,c16,b14,d15,a14, c15,b13 s_d[26:0] cmos i/o-ts 12ma xpressflow bus C data bit [26:0] b12 s_msgen# cmos i/o-ts 12 ma xpressflow bus C message envelope a12 s_eof# cmos i/o-ts 12ma xpressflow bus C end of frame c14 s_irdy cmos i/o-ts 12 ma xpressflow bus C initiator ready c13 s_tabt# cmos i/o-od 12 ma xpressflow bus C target abort b23 s_hpreq# cmos i/o-od 12ma xpressflow bus C high priority request a24 s_req# cmos output 4ma xpressflow bus C bus request to sc201 b24 s_gnt# cmos input xpressflow bus C bus grant from sc201 a13 s_ovld# cmos input xpressflow bus C bus overload d13 s_clk cmos input xpressflow bus C clock
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 5 rev.2.1 C february, 1999 pin no(s). symbol type name and functions control buffer memory interface m4,n2,l3,m1,m2,l1,k3, l2,k4,k1,j3,k2,j1,j2, h3,h1,h2,g3,g1,g2,f1,f3,f 2,e1,e3,e2,d1,d3,d2,c1,c2, b1 l_d[31:0] ttl i/o-ts 8ma local memory bus C data bit [31:0] a6,b6,c8,a7,d8,d7,c9, a8,b8,a9,c10,b9,d10, a10,c11,b10,a11 l_a[18:2] cmos output 8ma local memory bus C address bit [17:2] c7 l_a[19] / l_oe[3]# cmos output 8ma local memory bus C address bit [19] or memory read chip select [3] d5,a5,a3 l_o e[2:0]# cmos output 2ma local memory read chip select [2:0] d7,e4,b5,c4 l_we[3:0]# cmos output 2ma local memory write chip select [3:0] c6,b4,a4,c5 l_bwe[3:0]# cmos output 8ma local memory byte write enable, byte [3:0] b3 l_adsc# cmos output 8ma local memory controller address status g4 l_clk cmos output 8ma local memory clock input ethernet access port cont. [7:0] af20,ae17,ad12,ad9, ac2,t25 t[7:2]_rxd ttl in (5vt) receive data C (one for each 10mbps serial in- terface port) ac25,af6 t[1:0]_rxd ttl in (5vt) ad19,ad16,ae14,af10,ac2 1u24 t[7:2]_rxc ttl in (5vt) receive clock C (one for each 10mbps serial in- terface port) ac24,ae7 t[1:0]_rxc ttl in (5vt) af18,ad14,ae12,af8, w2,aa25,ae22,ad1 t[7:0]_txc ttl in (5vt) transmit clock C (one for each 10mbps serial in- terface port) ae19,af15,af12,ad8, w1,aa24 t[7:2]_txen cmos out 4ma transmit enable C (one for each 10mbps serial interface port) af22,af2 t[1:0]_txen cmos output ae20,af16,af13,ae10, y1,w25 t[7:2]_txd cmos out 4ma transmit data C (one for each 10mbps serial in- terface port) af23,ae4 t[1:0]_txd cmos output ad18,ad15,ae13,af9, y2,y26 t[7:2]_lpbk cmos out 2ma loop back enable C (one for each 10mbps serial interface port) ae23,af3 t[1:0]_lpbk cmos output af19,ae16,ad11,ae9, v3,aa26 t[7:2]_fd cmos out 2ma full duplex mode C (one for each 10mbps serial interface port) ad21,ae3 t[1:0]_fd cmos output ad17,ae15,af11,ae8, v1,ab26 t[7:2]_col ttl in (5vt) collision detected C (one for each 10mbps serial interface port) ad20,ac23 t[1:0]_col ttl in (5vt) ae18,ad13,ad10,ad7, u3,ab24, t[7:2]_crs ttl in (5vt) carrier sense C (one for each 10mbps serial in- terface port) af21,ad2 t[1:0]_crs ttl in (5vt) af17,af14,ae11,af7, v2,ab25, t[7:2]_lnk ttl in (5vt) link status C (one for each 10mbps serial inter- face port) ae21,ab3 t[1:0]_lnk ttl in (5vt)
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 6 rev.2.1 C february, 1999 pin no(s). symbol type max i ol / i oh name & functions test facility a25 t_mode cmos i/o-ts 2ma test pin C set test mode upon reset, and pro- vides test status output during test mode n1,m3,p2,p1,n3,r2,p3,r1,t 2r3,t1,r4,u2,t3,u1,u4 t_d[15:10] cmos output 4ma test pins C reserved for internal use only pin no(s). symbol type name & functions power pins d6,d11,d16,d21,f4, f23,l4,l23,t4,t23,aa4,aa23 ac6,ac11,ac16,ac21 vdd power +3.3 volt dc supply a1,a2,a26,b2,b25,b26, c3,c24,d4,d9,d14,d19,d23, h4,j23,n4,p23,v4,w23,ac4, ac8,ac13, ac18,ac23,ad3,ad24, ae1,ae2,ae25,af1, af25 vss power ground
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 7 rev.2.1 C february, 1999 1.3 pin reference table: (352 pin bga) pin # signal name pin # signal name pin # signal name pin # signal name pin # signal name f26 p_a[1] c18 s_d[13] e3 l_d[7] v1 t3_col t2 t_d[7] g24 p_a[2] b17 s_d[14] e1 l_d[8] v3 t3_fd r1 t_d[8] e25 p_a[3] a18 s_d[15] f2 l_d[9] y2 t3_lpbk p3 t_d[9] e26 p_a[4] b18 s_d[16] f3 l_d[10] y1 t3_txd r2 t_d[10] f24 p_a[5] c19 s_d[17] f1 l_d[11] w1 t3_txen n3 t_d[11] d25 p_a[6] a19 s_d[18] g2 l_d[12] w2 t3_txc p1 t_d[12] d26 p_a[7] b19 s_d[19] g1 l_d[13] ac1 t3_rxc p2 t_d[13] e24 p_a[8] c20 s_d[20] g3 l_d[14] ac2 t3_rxd m3 t_d[14] c25 p_a[9] a20 s_d[21] h2 l_d[15] af7 t4_lnk n1 t_d[15] d24 p_a[10] b20 s_d[22] h1 l_d[16] ad7 t4_crs c26 p_a[11] a21 s_d[23] h3 l_d[17] ae8 t4_col d6 vdd f25 p_ads# c21 s_d[24] j2 l_d[18] ae9 t4_fd d11 vdd g26 p_cs# d20 s_d[25] j1 l_d[19] af9 t4_lpbk d16 vdd h25 p_rwc b21 s_d[26] k2 l_d[20] ae10 t4_txd d21 vdd g25 p_bs16# a22 s_d[27] / p_c[4] j3 l_d[21] ad8 t4_txen f4 vdd j24 p_rdy# c22 s_d[28] / p_c[3] k1 l_d[22] af8 t4_txc f23 vdd j26 p_rst# b22 s_d[29] / p_c[2] k4 l_d[23] af10 t4_rxc l4 vdd h26 p_int a23 s_d[30] / p_c[1] l2 l_d[24] ad9 t4_rxd l23 vdd k24 p_clk c23 s_d[31] / p_c[0] k3 l_d[25] ae11 t5_lnk t4 vdd p25 p_d[0] l1 l_d[26] ad10 t5_crs t23 vdd p26 p_d[1] a11 l_a[2] m2 l_d[27] af11 t5_col aa4 vdd r24 p_d[2] b10 l_a[3] m1 l_d[28] ad11 t5_fd aa23 vdd n25 p_d[3] c11 l_a[4] l3 l_d[29] ae13 t5_lpbk ac6 vdd n26 p_d[4] a10 l_a[5] n2 l_d[30] af13 t5_txd ac11 vdd p24 p_d[5] d10 l_a[6] m4 l_d[31] af12 t5_txen ac16 vdd m25 p_d[6] b9 l_a[7] ae12 t5_txc ac21 vdd n24 p_d[7] c10 l_a[8] ab3 t0_lnk ae14 t5_rxc a1 gnd m26 p_d[8] a9 l_a[9] ad2 t0_crs ad12 t5_rxd a2 gnd l25 p_d[9] b8 l_a[10] ac3 t0_col af14 t6_lnk a26 gnd m24 p_d[10] a8 l_a[11] ae3 t0_fd ad13 t6_crs b2 gnd l26 p_d[11] c9 l_a[12] af 3 t0_lpbk ae15 t6_col b25 gnd k25 p_d[12] b7 l_a[13] ae4 t0_txd ae16 t6_fd b26 gnd l24 p_d[13] d8 l_a[14] af2 t0_txen ad15 t6_lpbk c3 gnd k26 p_d[14] a7 l_a[15] ad1 t0_txc af16 t6_txd c24 gnd j25 p_d[15] c8 l_a[16] ae7 t0_rxc af15 t6_txen d4 gnd b6 l_a[17] af6 t0_rxd ad14 t6_txc d9 gnd d13 s_clk a6 l_a[18] ae21 t1_lnk ad16 t6_rxc d14 gnd a13 s_ovld# c7 l_a[19] / oe[3]# af21 t1_crs ae17 t6_rxd d19 gnd b23 s_hpreq# d5 l_oe[2]# ad20 t1_col af17 t7_lnk d23 gnd a24 s_req# a5 l_oe[1]# ad21 t1_fd ae18 t7_crs h4 gnd b24 s_gnt# a3 l_oe[0] ae23 t1_lpbk ad17 t7_col j23 gnd b12 s_msgen# d7 l_we[3]# af23 t1_txd af19 t7_fd n4 gnd a12 s_eof# e4 l_we[2]# af22 t1_txen ad18 t7_lpbk p23 gnd c14 s_irdy b5 l_we[1]# ae22 t1_txc ae20 t7_txd v4 gnd c13 s_tabt# c4 l_we[0]# ac24 t1_rxc ae19 t7_txen w23 gnd b13 s_d[0] c6 l_bwe[3]# ac25 t1_rxd af18 t7_txc ac4 gnd c15 s_d[1] b4 l_bwe[2]# ab25 t2_lnk ad19 t7_rxc ac8 gnd a14 s_d[2] a4 l_bwe[1]# ab24 t2_crs af20 t7_rxd ac13 gnd d15 s_d[3] c5 l_bwe[0]# ab26 t2_col ac18 gnd b14 s_d[4] b3 l_adsc# aa26 t2_fd a25 t_mode ac23 gnd c16 s_d[5] g4 l_clk y26 t2_lpbk ad3 gnd a15 s_d[6] b1 l_d[0] w25 t2_txd u4 t_d[0] ad24 gnd b15 s_d[7] c2 l_d[1] aa24 t2_txen u1 t_d[1] ae1 gnd a16 s_d[8] c1 l_d[2] aa25 t2_txc t3 t_d[2] ae2 gnd c17 s_d[9] d2 l_d[3] u24 t2_rxc u2 t_d[3] ae25 gnd b16 s_d[10] d3 l_d[4] t25 t2_rxd r4 t_d[4] af1 gnd d17 s_d[11] d1 l_d[5] v2 t3_lnk t1 t_d[5] af25 gnd a17 s_d[12] e2 l_d[6] u3 t3_crs r3 t_d[6] note: output signals with programmable polarity. input or output pins with weak internal pull up resistors (50k to 100k ohms each) these pins are reserved for internal use only. they should be left unconnected.
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 8 rev.2.1 C february, 1999 2. functional description 2.1 local memory (local buffer memory) interface uses industry standard synchronous burst mode sram up to 1m bytes 9 32k x 32, 64k x 32, 128k x 32, or 256k x 32 provides separate read and write chip selects ( l_oe[3:0]# and l_we[3:0]# ) for each memory chip supports back to back read or write operations across memory chips 2.1.1 pin description symbol type name and functions l_d[31:0] ttl i/o-ts local memory data bus bit [31:0] C a 32-bit synchronous data bus. l_a[18:2] cmos output local memory address bus bit [18:2] C bit [18:2] of a synchronous address bus. the memory address is sampled when l_cs# is enabled and l_adsc# is asserted. l_a[19] / l_oe[3]# cmos output local memory address bus bit [19] or local memory read chip select [3] C de- pends on memory configuration, this pin can be used as the local memory address bit [19] or as the local memory read chip select [3]. l_oe[2:0]# cmos output local memory read chip select [2:0] C allows up to read one of the 4 banks of mem- ory. l_we[3:0]# cmos output local memory write chip select [3:0] C allows up to write one of the 4 banks of mem- ory. l_bwe[3:0]# cmos output local memory byte write enable [3:0] C use to write individual bytes. l_adsc# cmos output local memory controller address status C to load a new address. l_clk cmos output local memory clock C a synchronous clock to memory devices. l_d[31:0] ttl i/o-ts local memory data bus bit [31:0] C a 32-bit synchronous data bus. l_a[18:2] cmos output local memory address bus bit [18:2] C bit [17:2] of a synchronous address bus. the memory address is sampled when l_cs# is enabled and l_adsc# is asserted. l_a[19] / l_we[3]# cmos output local memory address bus bit [19] or local memory write chip select [3] C de- pends on memory configuration, this pin can be used as the local memory address bit [19] or as the local memory write chip select [3]. l_we[2:0]# cmos output local memory write chip select [2:0] C allows up to write one of the 4 banks of mem- ory. l_oe[3:0]# cmos output local memory read chip select [3:0] C allows up to read one of the 4 banks of mem- ory. l_bwe[3:0]# cmos output local memory byte write enable [3:0] C use to write individual bytes. l_adsc# cmos output local memory controller address status C to load a new address. l_clk cmos output local memory clock C a synchronous clock to memory devices. note: these pins have weak internal pull up resistors (50k to 100k ohms each).
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 9 rev.2.1 C february, 1999 2.1.2 supported memory configurations read/write chip select and high address bits chip #3 chip #2 chip #1 chip #0 ram chip size # of ram chips total buffer memory size l_we[3]# l_a[19] / l_oe[3]# l_we[2]# l_oe[2]# l_we[1]# l_oe[1]# l_we[0]# l_oe[0]# 32k x 32 1 128k bytes ---- ---- ---- ---- ---- ---- l_we[0]# l_oe[0]# 2 256k bytes ---- ---- ---- ---- l_we[1]# l_oe[1]# l_we[0]# l_oe[0]# 4 512k bytes l_we[3]# l_oe[3]# l_we[2]# l_oe[2]# l_we[1]# l_oe[1]# l_we[0]# l_oe[0]# 64k x 32 1 256k bytes ---- ---- ---- ---- ---- ---- l_we[0]# l_oe[0]# 2 512k bytes ---- ---- ---- ---- l_we[1]# l_oe[1]# l_we[0]# l_oe[0]# 4 1m bytes l_we[3]# l_oe[3]# l_we[2]# l_oe[2]# l_we[1]# l_oe[1]# l_we[0]# l_oe[0]# 128k x32 1 512k bytes ---- ---- ---- ---- ---- ---- l_we[0]# l_oe[0]# 2 1m bytes ---- ---- ---- ---- l_we[1]# l_oe[1]# l_we[0]# l_oe[0]# 256k x32 1 1m bytes ---- l_a[19] ---- ---- ---- ---- l_we[0]# l_oe[0]# 2.1.3 bus cycle waveforms a 1 a 2 a 3 a 3+1 a 3+2 a 3+3 a 4 a 4+1 a 4+2 a 4+3 a 5 a 6 d2 d3+1 d3+2 d3+3 d4 d4+1 d4+2 d4+3 d5 d6 d1 d3 l_clk l_adsc# l_cs# l_a[19:2] l_we[3:0]# l_bwe[3:0]# l_oe[3:0]# l_d[31:0] (wr) l_d[31:0] (rd) typical local memory access operations
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 10 rev.2.1 C february, 1999 2.2 processor bus interface supports various industry standard micro-processors including: 9 intel 186, 386, and 486 family or equivalent 9 motorola mpc series embedded processors easily adapts to other industry standard cpus provides separate address and data bus supports big & little endian byte ordering supports 16-bit data bus supports early rdy cycle 9 meets timing requirement for intel/amd 186 family proc- es sors supports 1x or 2x cpu clock 9 2x cpu clock for 386 family processors provides a single interrupt signal to switch manager cpu 2.2.1 pin description symbol type name and functions p_c[4:0] cmos input processor configuration bit [4:0] : C during the reset cycle, the p_c[4:0] pins provides the processor configuration. by using external weak pull-up or -down resistors, they define the ex- ternal management bus interface configuration. these inputs are sampled at the trailing edge of the reset cycle. c[0] C defines the cpu clock input is 1x or 2x clock c[1] C selects either big or little endian byte ordering c[2] C defines the polarity of the p_rwc (rd/wr control) input c[3] C defines the cpu bus width C for ea-208, it is default to 16-bit cpu bus interface, and the setting of this bit is ignored. c[4] C defines the timing relationship between p_rdy and p_d[15:0] valid. if c[4] is high, the p_d[15:0] are valid along in the same clock period as p_rdy is asserted. if c[4] is low, the p_rdy is asserted one clock period early ahead of the p_d[15:0] are valid. c[0] c[1] c[2] c[3] c[4] cpu clock byte order rwc bus size rdy timing lo 1x clock little en dian p_r/w# n/a normal hi 2x clock big endian p_w/r# n/a early after reset, these pins are used as xpressflow bus data bit [31:27]. p_a[11:1] ttl in (5vt) address bus bit [11:1 ] C i/o port address p_d[15:0] ttl i/o-ts (5vt) data bus bit [15:0] C a 16-bit synchronous data bus. p_ads# ttl in (5vt) address strobe C indicates valid address is on the bus p_rwc ttl input (5vt) read/write control C indicates the current bus cycle is a read or write cycle. c[1] defines the polarity of this signal during the reset cycle. c[1]=low p_r/w# is used for powerpc or other similar processors. c[1]=high p_w/r# is used for 386, 486 or other similar processors p_rdy# ttl out-od data ready C timing indicates for bus data valid p_bs16# ttl out-od bus size 16 C response to bus master that the ea208 only supports 16-bit data bus width. p_cs# ttl input (5vt) chip select C indicates the xpressflow engine is the target for the current bus operation. p_int cmos output interrupt request to switch manager cpu the polarity of this signal output is programmable via chip configuration register . p_rst# ttl in-st (5vt) cpu reset C synchronous reset input from switch manager cpu p_clk ttl in (5vt) cpu clock C 2x clock for 386 family, and 1x clock for the others
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 11 rev.2.1 C february, 1999 2.2.2 motorola mpc801 processor interface p_clk {clkout} p_ads# {ts#} p_a[11:1] {a[20:30]} p_cs# p_rwc {rd/wr#} p_rdy# {ta#} p_d[15:0] {d[0:15]} p_d[15:0] {d[0:15]} (out) (in) note: mnemonics with in {} are the equivalent signals defined by mpc801 typical motorola mpc801 cpu i/o access operations 2.2.3 intel 486 processor interface p_clk p_ads# p_a[11:1] p_cs# p_w/r# p_rdy# p_d[15:0] (in) p_d[15:0] (out) typical 486 cpu i/o access operations
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 12 rev.2.1 C february, 1999 2.2.4 intel 386 processor interface ph2 p_clk ph2 (internal) p_ads# p_a[11:1] p_cs# p_w/r# p_rdy# p_d[15:0] (in) p_d15:0] (out) typical 386 cpu i/o access operations ph2 ph1 ph2 or ph1 ph2 p_clk ph2 (internal) p_rst# internal ph2 clock synchronization ** note: ** see intel 386 processor data book for more details
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 13 rev.2.1 C february, 1999 2.2.5 register map note: all 32-bit registers are d-word aligned. all 16-bit registers are also d-word aligned and right justified. for the little endian cpus, register offset bit [1,0] are always set to be 00. for the big endian cpus, register offset bit [1,0] are always set to be 10. this is a global register. cpu is allowed to write the global register of all devices by a single operation. these registers are reserved for system diagnostic usage only. i/o offset register description little endian big endian reg. size w/r note: device configuration registers (dcr) gcr global control register hf00 hf02 16-bit w/-- dcr0 device status register hf00 hf02 16-bit --/r dcr1 signature & revision register hf10 hf12 16-bit --/r dcr2 id register hf20 hf22 16-bit w/r dcr3 device configuration register hf30 hf32 16-bit w/r dcr4 interfaces status register hf40 hf42 16-bit --/r dtsr test register hf70 hf72 16-bit w/r interrupt controls isr interrupt status register C unmasked hf80 hf82 16-bit --/r isrm interrupt status register C masked hf90 hf92 16-bit --/r imsk interrupt mask register hfa0 hfa2 16-bit w/r iar interrupt acknowledgment register hfb0 hfb2 16-bit w/-- buffer memory interface mwar memory write address reg. C single cycle he08 he08 32-bit w/r mrar memory read address reg. C single cycle he18 he18 32-bit w/r mbar memory address register C burst mode he28 he28 32-bit w/r mwbs memory write burst size (in d-words) he40 he42 16-bit w/r mrbs memory read burst size (in d-words) he50 he52 16-bit w/r mwdr memory write data register he68 he68 32-bit w/-- mwdx memory write data reg. C byte swapping he6c he6c 32-bit w/-- mrdr memory read data register he68 he68 32-bit --/r mrdx memory read data reg. C byte swapping he6c he6c 32-bit --/r fcb buffer & stack management fcbba frame control buffer C base address hd00 hd02 16-bit w/r fcbag frame control buffer C buffer aging status hd30 hd32 16-bit --/r fcbsl frame ctrl buffer stack C size limit hd90 hd92 16-bit w/r fcbst frame ctrl buffer stack C buffer low threshold hda0 hda2 16-bit w/r fcbss frame ctrl buffer stack C allocation status hdb0 hdb2 16-bit --/r
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 14 rev.2.1 C february, 1999 i/o offset register description little endian big endian reg. size w/r note: access control function (chip level controls) avxr vlan control table (vct) index register hc00 hc02 16-bit w/-- avdr vct data register hc10 hc12 16-bit w/r avtc vlan type code hc20 hc22 16-bit w/r axsc transmission scheduling control register hc30 hc32 16-bit w/r amiic mii command register hc40 hc40 32-bit w/-- amiis mii status register hc40 hc40 32-bit --/r afcr flow control register hc70 hc72 16-bit w/r amar0 multicast address. for mac control frames byte [1,0] hc80 hc82 16-bit w/r amar1 byte [3,2] hc90 hc92 16-bit w/r amar2 byte [5,4] hca0 hca2 16-bit w/r amct mac control frametype code register hcb0 hcb2 16-bit w/r adar0 base mac address register C byte [1,0] hcc0 hcc2 16-bit w/r adar1 base mac address register C byte [3,2] hcd0 hcd2 16-bit w/r adar2 base mac address register C byte [5,4] hce0 hce2 16-bit w/r ethernet mac port control registers C (substitute [n] with port number, n = {0..3] ) ecr0 mac port control register h n 00 h n 02 16-bit w/r ecr1 mac port configuration register h n 10 h n 12 16-bit w/r ecr2 mac port interrupt mask register hn20 hn22 16-bit w/r ecr3 mac port interrupt status register hn30 hn32 16-bit --/r exsr mac tx status register hn40 hn42 16-bit --/r exec mac tx error counters hn50 hn52 16-bit --/r ersr mac rx status register hn68 hn68 32-bit --/r erec mac rx error counters hn78 hn78 32-bit --/r
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 15 rev.2.1 C february, 1999 2.3 xpressflow bus operation zarlink s optimized xpressflow bus architecture provides 1.6g bps switching bandwidth 9 -33 1.07g bps 9 -40 1.28g bps 9 -50 1.6g bps full multi bus master structure allows xpressflow engine to communicate with access con- trollers via a message passing protocol 9 command messages for passing control information be- tween devices 9 data messages for forwarding an ethernet frame from re- ceiving port to transmission port built-in intelligent bus load regulator for data traffic balancing provides centralized bus arbitration with two level request pri- orities 9 high priority for data messages 9 low priority for command messages 2.3.1 pin description symbol type name and functions s_d[31:0] cmos i/o-ts data bus bit [31:0] C a 32-bit synchronous data bus. note: during the system reset period, data bit [31:28] are used as processor interface configuration bit [0:3] s_msgen# cmos i/o-ts message envelope C encompasses the entire period of a message transfer. targets use the leading edge of this signal to detect the beginning of a message transfer, and to decode the message header for the intended target(s). s_eof# cmos i/o-ts end of frame C only used by frame data transfer messages to identify the end of frame condi- tion. this signal is synchronous with the rx frame status word appended to the end of the message. s_irdy cmos i/o-ts initiator ready C a normal true signal. when negated, it indicates the initiator had asserted wait state(s) in between command words. target should use this signal as enable signal for latching the data from the bus. s_tabt# cmos i/o-od target abort C when asserted, the target had aborted the reception of current message on the bus. s_hpreq# cmos i/o-od high priority request C indicates one or more bus requester is requesting for high priority message transfer. s_req# cmos output bus request Cbus request signals from access controller to bus access arbitrator in xpress- flow engine s_gnt# cmos in- put bus grant Cbus grant signals from bus arbitrator to bus requester s_ovld# cmos output bus overload C when asserted, all data forwarding bus bandwidth has been allocated. cannot support additional load for data forwarding traf fic. s_clk cmos input xpressflow bus clock C 33mhz system clock
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 16 rev.2.1 C february, 1999 2.3.2 bus cycle waveforms c0 d5 eof d2 c1 d0 d1 d3 d4 s_clk s_msgen# s_d[31:0] s_eof# s_irdy xpressflow bus data transfer cycle command cycle data xfer w/o data c0 c1 c0 c1 eof c1 c0 aborted command s_clk s_msgen# s_d[31:0] s_eof# s_tabt# other xpressflow bus cycles s_clk s_req[k]# s_req[j]# s_hpreq# high priority request pre-empts the low priority request.
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 17 rev.2.1 C february, 1999 s_clk s_msgen# s_req[j]# s_gnt[j]# s_hpreq# s_req[i]# s_gnt[i]# xpressflow bus arbitration s_clk s_req[k]# s_ovld# bus overload pre-empts the data transfer request
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 18 rev.2.1 C february, 1999 2.4 10mb serial interface for port 0 through 7 fully compliant with ieee 802.3 10m bit serial interface stan- dard for connecting with external 10mbps ethernet physical layer transceiver supports 10mbps 10baset serial interface supports both half and full duplex operation 2.4.1 pin description symbol type name and functions tn_rxd ttl in (5vt) receive data C (one for each 10m bit serial interface port) a receive data stream. tn_rxc ttl in (5vt) receive clock C (one for each 10m bit serial interface port) from external phy for sampling the receive data from tn_rxd input tn_txc ttl in (5vt) transmit clock C (one for each 10m bit serial interface port) a continuous clock input with 35% to 65% duty cycles. tn_txen cmos output transmit enable C (one for each 10m bit serial interface port) tn_txd cmos output transmit data C (one for each 10m bit serial interface port) a transmit data stream. tn_lpbk cmos output loop back enable C (one for each 10m bit serial interface port) the polarity of this signal is programmable via port configuration register tn_fd cmos output full duplex mode C (one for each 10m bit serial interface port) the polarity of this signal is programmable via port configuration register tn_col ttl in (5vt) collision detected C (one for each 10m bit serial interface port) tn_crs ttl in (5vt) carrier sense C (one for each 10m bit serial interface port) tn_lnk ttl in (5vt) link status C (one for each 10m bit serial interface port) the polarity of this signal is pro- grammable via port configuration register note : n is the port number [7:0] these signals have programmable output polarity. 100 nsec 100 nsec txc txen txd 10m bit serial interface C transmit timing
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 19 rev.2.1 C february, 1999 100 nsec 100 nsec crs rxc rxd 10m bit serial interface C receive timing 2.5 test pins symbol type name and functions t_mode cmos i/o-ts test mode selection & test output C set test mode upon reset, and provides test status output during test mode
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 20 rev.2.1 C february, 1999 3. dc specification 3.1 absolute maximum ratings storage temperature -50 c to +125 c operating temperature 0 c to +70 c supply voltage v dd with respect to v ss +3.0 v to +3.6 v voltage on 5v tolerant input pins -0.5 v to (v dd + 1.8 v) voltage on other input pins -0.5 v to (v dd + 10%) stresses above those listed may cause permanent device failure. functionality at or above these limits is not implied. exposu re to ab- solute maximum ratings for extended periods may affect device reliability. 3.2 dc characteristics v dd = +3.0 v to +3.6 v t ambient = 0 c to +70 c preliminary symbol parameter description min type max unit f osc frequency of operation (-40) 20 40.0000 mhz frequency of operation (-50) 20 50.0000 mhz frequency of operation (-66) 20 66.6667 mhz i dd supply power C @ 40 mhz (v dd =3.3 v) 300 500 ma supply power C @ 50 mhz (v dd =3.3 v) 300 500 ma supply power C @ 66.67 mhz (v dd =3.3 v) 360 600 ma v oh-cmos output high voltage (cmos) i oh = maximum v dd - 0.5 v v ol-cmos output low voltage (cmos) i ol = maximum 0.45 v v oh-ttl output high voltage (ttl) i oh = maximum 2.4 v v ol-ttl output low voltage (ttl) i ol = maximum 0.45 v v ih-cmos input high voltage (cmos) vdd x 70% v dd + 10% v v il-cmos input low voltage (cmos) -0.5 vdd x 30% v v ih-ttl input high voltage (ttl) 2.0 v dd + 10% v v il-ttl input low voltage (ttl) -0.3 +0.8 v v ih-5vt input high voltage (ttl 5v tolerant) 2.0 v dd + 1.8 v v il-5vt input low voltage (ttl 5v tolerant) -0.3 +0.8 v i li input leakage current (0.1 v ) v in ) v dd ) (all pins except those with internal pull-up/pull-down resis- tors) 10 a i lo output leakage current (0.1 v ) v out ) v dd ) 15 a i ih input leakage current v ih = v dd - 0.1 v (pins with internal pull-down resistors) 60 a i il input leakage current v il = 0.1 v (pins with internal pull-up resistors) -60 a c in input capacitance 8 pf c out output capacitance 8 pf c i/o i/o capacitance 10 pf notes:
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 21 rev.2.1 C february, 1999 4. ac specification 4.1 xpressflow bus interface: s17 s19 s21 s23 s27 s29 s31 s33 s18 s20 s22 s24 s28 s30 s32 s34 s_clk s_d[31:0] s_msgen# s_eof# s_irdy s_tabt# s_hpreq# s_gnt# s_ovld# xpressflow bus interface C input setup and hold timing s1-min s12 s2-min s13 s3-min s14 s4-min s15 s_clk s_d[31:0] s_msgen# s_eof# s_irdy xpressflow bus interface C output float delay timing s1-min s1-max s2-min s2-max s3-min s3-max s4-min s4-max s6-min s6-max s7-min s7-max s8-min s8-max s_clk s_d[31:0] s_msgen# s_eof# s_irdy s_tabt# s_hpreq# s_req# xpressflow bus interface C output valid delay timing
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 22 rev.2.1 C february, 1999 -40 -50 -66 symbol parameter min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) note: s1 s_d[31:0] output valid delay 6 14 5 11 4 8.5 c l = 50pf s2 s_msgen# output valid delay 6 14 5 11 4 8.5 c l = 50pf s3 s_eof# output valid delay 6 14 5 11 4 8.5 c l = 50pf s4 s_irdy output valid delay 6 14 5 11 4 8.5 c l = 50pf s6 s_tabt# output valid delay 6 14 5 11 4 8.5 c l = 50pf s7 s_hpreq# output valid delay 6 14 5 11 4 8.5 c l = 50pf s8 s_req# output valid delay 6 14 5 11 4 8.5 c l = 20pf s12 s_d[31:0] output float delay 18 15 12 s13 s_msgen# output float delay 18 15 12 s14 s_eof# output float delay 18 15 12 s15 s_irdy output float delay 18 15 12 s17 s_d[31:0] input set-up time 2 1.5 1 s18 s_d[31:0] input hold time 5.5 4.5 3.5 s19 s_msgen# input set-up time 2 1.5 1 s20 s_msgen# input hold time 5.5 4.5 3.5 s21 s_eof# input set-up time 2 1.5 1 s22 s_eof# input hold time 5.5 4.5 3.5 s23 s_irdy input set-up time 2 1.5 1 s24 s_irdy input hold time 5.5 4.5 3.5 s27 s_tabt# input set-up time 13 10 8 s28 s_tabt# input hold time 5.5 4.5 3.5 s29 s_hpreq# input set-up time 2 1.5 1 s30 s_hpreq# input hold time 5.5 4.5 3.5 s31 s_gnt# input set-up time 13 10 8 s32 s_gnt# input hold time 5.5 4.5 3.5 s33 s_ovld# input set-up time 15 12 9 s34 s_ovld# input hold time 5.5 4.5 3.5 ac characteristics C xpressflow bus interface
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 23 rev.2.1 C february, 1999 4.2 cpu bus interface: p16-min p15 p_clk p_d[31:0] cpu bus interface C output float delay timing p16-min p16-max p17-min p17-max p18-min p18-max p_clk p_d[15:0] p_rdy# p_int cpu bus interface C output valid delay timing p1 p3 p5 p7 p9 p11 p2 p4 p6 p8 p10 p12 p_clk p_rst # p_ads# p_w/r# p_cs# p_a[11:1] p_d[15:0] cpu bus interface C input setup and hold timing -40 -50 -66 symbol parameter min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) note: p1 p_rst# input setup time 13 10 8 p2 p_rst# input hold time 3.5 2.5 2 p3 p_ads# input set-up time 13 10 8 p4 p_ads# input hold time 3.5 2.5 2 p5 p_w/r# input set-up time 13 10 8 p6 p_w/r# input hold time 3.5 2.5 2 p7 p_cs# input set-up time 13 10 8 p8 p_cs# input hold time 3.5 2.5 2 p9 p_a[11:1] input set-up time 13 10 8 p10 p_a[11:1] input hold time 3.5 2.5 2 p11 p_d[31:0]# input set-up time 13 10 8 p12 p_d[31:0]# input hold time 3.5 2.5 2 p15 p_d[31:0]# output float delay 17 13 10 p16 p_d[31:0]# # output valid delay 8.5 6.5 5 c l = 60pf p17 p_rdy# output valid delay 8.5 6.5 5 c l = 60pf p18 p_int# output valid delay 17 13 10 c l = 20pf ac characteristics -- cpu bus interface
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller ? 1998 zarlink semiconductor, inc. 24 rev.2.1 C february, 1999 4.3 local memory interface: l1 l2 l_clk l_d[31:0] local memory interface C input setup and hold timing l3-min l10 l_clk l_d[31:0] local memory interface C output float delay timing l3-min l3-max l4-min l4-max l5-min l5-max l6-min l6-max l7-min l7-max l8-min l8-max l9-min l9-max l_clk l_d[31:0] l_a[19:2] l_cs[3:0]# l_adsc# l_bwe[3:0]# l_we#] l_oe# local memory interface C output valid delay timing -40 -50 -66 symbol parameter min (ns) max (ns) min (ns) max (ns) min (ns) max (ns) note: l1 l_d[31:0]# input set-up time 6.5 5.5 4 l2 l_d[31:0]# input hold time 3 2.5 2 l3 l_d[31:0]# output valid delay 17 13 10 c l = 30pf l4 l_a[19:2] output valid delay 17 13 10 c l = 30pf l6 l_adsc# output valid delay 17 13 10 c l = 30pf l7 l_bwe[3:0]# output valid delay 17 13 10 c l = 30pf l8 l_we# output valid delay 17 13 10 c l = 10pf l9 l_oe# output valid delay 17 13 10 c l = 10pf l10 l_d[31:0]# output float delay 22 18 14 ac characteristics C local memory interface
preliminary information xpressflow-2020 series C ea218e ethernet switch chipset 8-port 10mb ethernet access controller this document contains preliminary information on a product. zarlink semiconductor inc. reserves the right to make any changes w ithout notice. 5. packaging information 352-pin bga (35x35x2.33mm) a b 35.00 +/- 0.20 pin 1 i.d. 2.33 +/-0.13 0.60 +/-0.10 c 31.75 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1.27 2 4 1 3 6 8 5 7 10 12 9 11 20 19 18 17 14 16 13 15 22 26 25 23 21 24 0.75 dia +/- 0.15 (352x) 1.17 ref 0.56 ref 32.00 ref 24.00 ref ordering information part number description identification zarlink use revision ea218e 8-port 10mbps ethernet network access c0 b tav rrr environmental C c = commercial revision - 001 = rev.1 i = industrial for latest revision, leave blank speed grade - 0 = 40 mhz 5 = 50 mhz 6 = 66 mhz package - b = bga ? 1998 zarlink semiconductor inc. 400 march road o ttawa, ontario, canada k2k 3h4 rev. 2.1 february 1999 tel. 613 592 0200, fax: 613 592 1010 web site: www.zarlink.com
c zarlink semiconductor 2002 all rights reserved. apprd. issue date acn package code previous package codes: dimension conforms to jedec ms - 034 e b e e1 a2 d d1 a a1 35.20 34.80 30.00 ref 352 1.27 0.60 0.90 30.00 ref 1.17 ref 34.80 min 0.50 2.20 35.20 2.46 0.70 max 6. substrate thickness is 0.56 mm 4. n is the number of solder balls 2. dimension "b" is measured at the maximum solder ball diameter 1. controlling dimensions are in mm 5. not to scale. 3. seating plane is defined by the spherical crowns of the solder balls. d e e d1 e1 a2 a1 a
www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at

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